An Efficient VLSI Architecture for PRESENT Block Cipher and its FPGA Implementation

Pandey, JG and Goel, T and Karmakar, A (2017) An Efficient VLSI Architecture for PRESENT Block Cipher and its FPGA Implementation. In: 21st VLSI Design and Test Symposium (VDAT-2017), 29 June 2017 - 02 July 2017, Roorkee. (Submitted)

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Abstract

Lightweight cryptography plays an essential role for emerging authen-tication-based pervasive computing applications in resource-constrained envi-ronments. In this paper, we have proposed resource-efficient and high perfor-mance VLSI architectures for PRESENT block cipher algorithm for the two key lengths 80-bit and 128-bit, namely PRESET-80 and PRESENT-128. The FPGA implementations of these architectures have been done on LUT-6 technology based Xilinx Virtex-5 XC5VFX70T -1-FF1136 FPGA device. These architec-tures have latency of 33 clock cycles, run at maximum clock frequency of 306.84 MHz and provide throughput of 595.08 Mbps. They have been compared with the two different established architectures. It has been observed that the PRESENT-80 architecture consumes 20.3% lesser FPGA slices and there is gain of 25.4% in throughput. Similarly, the PRESENT-128 architecture requires 20.7% lesser FPGA slices alongwith a reduction in the latency by 27.7% and an overall increase of throughput by 69.1%.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	Lightweight cryptography, PRESENT, block cipher, VLSI archi-tectures, FPGAs
Subjects:	Semiconductor Devices > IC Design
Divisions:	Semiconductor Devices
Depositing User:	Mr. Rohit Singh
Date Deposited:	11 Sep 2017 11:25
Last Modified:	11 Sep 2017 11:25
URI:	http://ceeri.csircentral.net/id/eprint/305

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