Design of Pseudo Flip-around Sample- Hold Circuit for 10-bit, 5-Msamples/Sec Pipeline ADC

Santosh, M and Behera, KC and Bose, SC (2009) Design of Pseudo Flip-around Sample- Hold Circuit for 10-bit, 5-Msamples/Sec Pipeline ADC. In: International Conference on Emerging Trends in Electronics & Photonic Devices & Systems (ELECTRO-2009), December 22-24, 2009, BHU, Varanasi. (Submitted)

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Abstract

This paper describes the design of a pseudo flip-around sample- hold circuit for a 10-bit, 5-Msamples/sec pipeline ADC.The sample-hold circuit is simulated in 0.35 μm Austria Microsystems technology with a 1 KHz, 1.2 Vp-p sinusoidal inputand a sampling clock of 5 MHz. The simulation shows a worst case sampling error of 1 mV, SNR of 60 dB. The layout of the sample hold circuit occupies an area of 0.007mm2 and consumes 1.7 mW ofpower.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	Sample-and-Hold, ADC, SNR, Flip-around
Subjects:	?? TK ?? Semiconductor Devices > IC Design
Divisions:	Semiconductor Devices
Depositing User:	Mr. Jitendra Nath Bajpai
Date Deposited:	21 May 2013 05:17
Last Modified:	21 May 2013 05:17
URI:	http://ceeri.csircentral.net/id/eprint/140

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