A Lifting Instruction for Performing DWT in LEON3 Processor based System-on-Chip


Downloads per month over past year

Bansal, R and Jatav, MK and Karmakar, A (2017) A Lifting Instruction for Performing DWT in LEON3 Processor based System-on-Chip. In: 21st VLSI Design and Test Symposium (VDAT-2017), 29 June 2017 - 02 July 2017, Roorkee. (Submitted)

Download (802Kb) | Preview


Discrete Wavelet Transform (DWT) calculations form an inherent part of many signal processing applications. Application specific instructions provide a means to increase performance and efficiency of System-on-Chip (SoC) requiring DWT operations. In this paper, lifting scheme based hardware for efficient DWT calculation, is implemented as an instruction to enhance the performance of an SoC. The hardware is integrated using the coprocessor interface of the SPARCv8 ISA based LEON3 processor. This method for attaching lifting hardware is found to be much more efficient than the prevalent system-bus based integration. The performance measure is provided in terms of CPI and MIPS along with FPGA and ASIC implementation results of the SoC.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Lifting Scheme, DWT, LEON3, SPARCv8, System-on-Chip, SoC
Subjects: Semiconductor Devices > IC Design
Divisions: Semiconductor Devices
Depositing User: Mr. Rohit Singh
Date Deposited: 11 Sep 2017 11:26
Last Modified: 11 Sep 2017 11:26
URI: http://ceeri.csircentral.net/id/eprint/306

Actions (login required)

View Item View Item