Saurav, S and Saini, R and Singh, S
(2018)
FPGA Based Implementation of Linear SVM for Facial Expression Classification.
In: 7th International Conference on Advances in Computing, Communications &Informatics, September 19-22, 2018, Bangaloru.
(Submitted)
Abstract
Ahstr‹ict— This work presents a Field Programmable Gate A i ray (FPGA) based hardware efficient implementation of One- Versus-.411 (OVA) linear Support Vector Machine (SVM) classifier for classifying the facial expressions on an individual. The motivation is to achieve a real-time classification ol’ the 1‘aciaI expressions ol’ an individual into three dif1’erent states viz., neutral, happy, and pain so that the designed architecture could be used as a part of an embedded platform based FER system mm the purpose of monitoring patients in hospitals. Thus, the design challenge is to achieve classification accuracy equix-alent to the software-based implementation with a multi-fold improvement in the execution time. The acceleration in the execution time of the designed classifier has been achieved utilizing the parallelism and pipelining concepts of the VLSI architecture design. Moreover, to reduce the computational cost and boost the execution speed of the architecture we have adopted the fixed-point data format (Q24.16) in our design. The classifier has been trained pffline and the parameters of the trained classifier have been used to perform testing using the designed architecture on hardware. The designed architecture u tter synthesis operates at a maximum clock frequency of 241.55 M Hz and is resource efficient. Classification accuracy of 98.50•Z» equivalent to its softw are counterpart has been achieved on simulating the designed architecture with different test images. Thus, the designed classifier architecture shows good performance in terms o1‘ speed, area, and accurac y, and is suitable for real-time classification of the facial expressions.
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