A Novel Design of SRAM using Memristors at 45 nm Technology


Downloads per month over past year

Louis, VJ and Pandey, JG (2019) A Novel Design of SRAM using Memristors at 45 nm Technology. In: 23rd International Symosium on VLSI Design and Test (VDAT-2019), July 04-06, 2019, IIT Indore, India.

Download (5Mb) | Preview


There is an ever-increasing need for low-cost, higher density, low-power and high-performance memory devices. Memristor is one of the most promising device for obtaining memories as it offers smaller area and lower con-sumption. In the proposed work memristor-based SRAM circuit has been de-signed by using 45 nm technology of Predictive Technology Model. The read time of 1-bit cell is 5 ps and the write time 7 ps. Total area of the cell is 3.861 micrometer square.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Memristors, SRAM, Memory Design
Subjects: Semiconductor Devices > IC Design
Divisions: Semiconductor Devices
Depositing User: Mr. Jitendra Nath Bajpai
Date Deposited: 27 Aug 2021 06:32
Last Modified: 27 Aug 2021 06:34
URI: http://ceeri.csircentral.net/id/eprint/462

Actions (login required)

View Item View Item