A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher

Pandey, JG and Goel, T and Karmakar, A (2019) A High-performance and Area-efficient VLSI Architecture for the PRESENT Lightweight Cipher. In: 17th international Conference on Embedded Systems & 31st International Conference on VLSI Design, Jan. 6-10, 2018, Pune, Maharashtra. (Submitted)

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Abstract

Abstract— Security and privacy are the prime concern in the emerging internet of things (IoT) and cyber-physical systems (CPS) based applications. Lightweight cryptography plays an essential role for securing the data in this emerging pervasive computing environ ments. In this paper, we propose a high- performance and area-efficient VLSI architecture with 64-bit datapath for the PRESENT block cipher. The proposed architecture performs an integrated encryption/decryption operation for both 80-bit and 128-bit key lengths. The architecture is synthesized for the Yirtex-5 XCSVLX 1 10T FPGA device, available on the Xilinx ML-505 platform. It has been observed that the proposed architecture utilizes 0.73% and 0.87% of FPGA slices for 80-bit and 128-bit key lengths respectively. A through put of 410 Mbps and power consumption is about 16 mW for both the key lengths.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	Keywords— Lightweight cryptography,- PRESENT block cipher,- Integrated eiicryptioMdecryption; VLSI architecture,- FPGAs.
Subjects:	Electronic Systems > Embedded Systems
Divisions:	Electronic Systems
Depositing User:	Mr. Rabin Chatterjee
Date Deposited:	04 Dec 2019 09:11
Last Modified:	04 Dec 2019 09:11
URI:	http://ceeri.csircentral.net/id/eprint/327

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