Silicon Nanoparticles for Floating Gate Memory Application

Prajesh, R and Kumar, S and Kumar, A (2011) Silicon Nanoparticles for Floating Gate Memory Application. In: 16th International Workshop on the Physics of Semiconductor Devices (IWPSD - 2011), December 19 - 22, 2011, IIT Kanpur, India. (Submitted)

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Abstract

In this paper we demonstrate memory application of silicon Nano particles. A MOS capacitor with nanoparticles sandwiched between tunneling and capping oxide was fabricated and characterized. Write ‘1’ and write ‘0’ operations are verified by C-V measurements. Flat-band voltage shift in the C-V Curves explains the charge storage behavior of MOS capacitor. Interface charges, flat band and threshold voltages are estimated using Poisson’s equation and numerical methods.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	Nano Particles(NP), Floating Gate Memory, threshold voltage shift, write ‘1’ & write ‘0’ operation.
Subjects:	Semiconductor Devices > Sensors and Nanotechnology
Divisions:	Semiconductor Devices
Depositing User:	Mr pvlr reddy
Date Deposited:	27 May 2013 10:04
Last Modified:	27 May 2013 10:04
URI:	http://ceeri.csircentral.net/id/eprint/205

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