Generation and Annihilation of Process Induced Deep Level Defects in MOS Structures

Shashank, N and Gupta, SK and Singh, V and Akhtar, J and Nahar, RK and Damle, R (2010) Generation and Annihilation of Process Induced Deep Level Defects in MOS Structures. In: National Conference on Electronic Technology (ECT 2010), April 16-17, 2010, Goa, India. (Submitted)

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Abstract

The deep-level traps in Si substrates induced during the processing of Ni/ SiO2/n-Si have been investigated using deep level transient spectroscopy (DLTS). A deep level trap was detected at EC -0.49 eV, which was estimated to beintroduced during high temperature thermal oxidation process. The trap position was found to shift to different energy levels (Ec-0.43 eV, Ec-0.46 eV and Ec-0.34eV) during annihilation process. The deep level traps completely annealed at 350oC. Significant reduction in trap density with a systematic increase in recombination life time and the substrate doping concentration as a function of isochronal annealing were observed. The relevant details are discussed in this paper.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	DLTS, Deep Levels, MOS, Oxidation, Process induced defects, Trap density.
Subjects:	?? TK ?? Semiconductor Devices > Sensors and Nanotechnology
Divisions:	Semiconductor Devices
Depositing User:	Mr. Jitendra Nath Bajpai
Date Deposited:	23 May 2013 08:42
Last Modified:	23 May 2013 08:42
URI:	http://ceeri.csircentral.net/id/eprint/82

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