A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations

Pandey , JG and Godel , T and Nayak , M and Mit harwa , C and Khan, S and Santosh, K and Singh, R and Karma, V and Karmakar, A (2018) A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations. In: 22nd International System on VLSI Design and Test (VDAT ), June 28-30, 2018, Tamil Nadu. (Submitted)

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Abstract

Abstract. The in frast ruct ure of intern et-of-th ings (IoT) and cyber-physical systems (CPS) is based on th e security of communicated dat a. Here , lig ht we ig ht cryptogra phy plays a vital role in IoT/ CPS reso urce-constra ined environments. In this paper, we propose an architecture for the PRESENT lightweight block cipher and its VLSI implement at ion in an FPGA and ASIC. The input-output ports of the chit lecture are registered and the data­ path is based on 8-bit. It requires 49 clock cycles for processing of 64-bit plaintext with 80-bit user key. The FPGA implementation of the pro­ posed architecture is done in Xilinx Virt ex-5 device in compar is on to an exist ing design improved per Forman ce has been obtained. Further, an ASIC imp element ion of the architecture is done in SCL 180 nm technol­ ogy where gate equivalent (GE) of the design is 1 608 GEs and the area of the chip is 1.55 mm2. At 100 MHz operating frequency, the total power consumption of the chip is 0.228 mW. A throughput of 130.612 Mbps, energy 112.15 nJ, energy / bit 14.018 nJ /bit, and 0.813 efficiencies are obtained.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	Keywords: PRESENT block cipher• Lightw eight cryptography• VLSI a rch it ectur e• FPGA • ASIC .
Subjects:	Semiconductor Devices > IC Design
Divisions:	Semiconductor Devices
Depositing User:	Mr. Rabin Chatterjee
Date Deposited:	27 Jul 2021 09:43
Last Modified:	27 Jul 2021 09:43
URI:	http://ceeri.csircentral.net/id/eprint/377

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