VLSI Architecture of Pairwise Linear SVM for Facial Expression Recognition

Saurav, S and Saini, AK and Singh, S and Saini, R and Gupta, S (2015) VLSI Architecture of Pairwise Linear SVM for Facial Expression Recognition. In: 4th International Conference on Advances in Computing, Communications & Informatics(ICACCI-2015), August 10-13, 2015, SCMS, Aluva, Kochi. (Submitted)

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Abstract

In this paper, we present VLSI architecture of Pairwise Linear Support Vector Machine (SVM) classifier for multi-classification on FPGA. The objective of this work is to facilitate real time classification of the facial expressions into three categories: neutral, happy and pain, which could be used in a typical patient monitoring system. Thus, the challenge here is to achieve good performance without compromising the accuracy of the classifier. In order to achieve good performance pipelining and parallelism (key methodologies for improving the performance/frame rates) have been utilized in our architectures. We have used pairwise SVM classifier because of its greater accuracy and architectural simplicity. The architectures has been designed using fixed-point data format. Training phase of the SVM is performed offline, and the extracted parameters have been used to implement testing phase of the SVM on the hardware. According to simulation results, maximum frequency of 241.55 MHz, and classification accuracy of 97.87% has been achieved, which shows a good performance of our proposed architecture.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	Support Vector Machines; Pairwise SVM; VLSI Architectures; Classification; LibSVM
Subjects:	Semiconductor Devices > IC Design
Divisions:	Semiconductor Devices
Depositing User:	Mr. Jitendra Nath Bajpai
Date Deposited:	12 Jan 2017 09:19
Last Modified:	12 Jan 2017 09:19
URI:	http://ceeri.csircentral.net/id/eprint/243

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