Silicon Nanowire Arrays using g-line Photolithography

Prajesh, R and Agarwal, A (2011) Silicon Nanowire Arrays using g-line Photolithography. In: 16th International Workshop on the Physics of Semiconductor Devices (IWPSD - 2011), December 19 - 22, 2011, IIT Kanpur, India. (Submitted)

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Abstract

1 and 2 micron wide silicon fin patterns realized using standard g-line UV lithography are oxidized to accomplish nanowires. Simulation results envisage the possibility of silicon nanowire fabrication using top down fabrication approach. Silicon consumption from three sides of the fins reduces their geometries. Stress developed in the oxide leads to a pinch-off in the fins with aspect ratios >3. This pinch-off divides the fin patterns into two parts vertically; upper part converges into silicon Nanowire, buried in silicon oxide. Simulation results for different process temperatures, time and fin aspect ratios are presented in the paper.

Item Type:	Conference or Workshop Item (Paper)
Uncontrolled Keywords:	Stress Dependent Oxidation, Pinch-off, Fin, Aspect Ratio, Silicon Nanowire
Subjects:	?? TK ?? Semiconductor Devices > MEMS and Microsensors
Divisions:	Semiconductor Devices
Depositing User:	Mr. Rohit Singh
Date Deposited:	22 May 2013 09:48
Last Modified:	22 May 2013 09:48
URI:	http://ceeri.csircentral.net/id/eprint/164

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