Mask Designing and Process Definition of Backside Contacted ISFET


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Yadav, NS and Nitharwal, M and Chaturvedi, A and Khanna, VK and Sharma, R and Mukhiya, R (2012) Mask Designing and Process Definition of Backside Contacted ISFET. In: National Conference on Recent Advances in Communications, Control and Computing Technology (RACCCT - 2012), March 29 - 30, 2012, Surat, Gujarat . (Submitted)

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A fabrication method for Ion-Sensitive Field-Effect Transistor (ISFET) structures is proposed. In this approach, external electrical contacts to the n+ source and drain regions are made through individual cavities etched from the backside and the sidewalls isolation will be provided in the cavities and metallization covering the sidewalls. The FET structure will be constructed on the front face of the chip. The connections between the source and the drain diffusion and the back contacts will be achieved by diffusing impurities from both sides of the wafer. The front surface will have an insulating surface where the chemically active gate will be placed. The device will thus act as a chemical sensor. This will contrast with traditional ISFET devices where the gate and the contacts are placed on the front surface of the transistor. These sensors will be more compact, easily mounted and there encapsulation is much easier as compared to conventional chemical sensors. However, the fabrication technology will be more complex.

Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: ISFETs, Back contacts, Deep Diffusion,
Subjects: ?? TK ??
Semiconductor Devices > MEMS and Microsensors
Divisions: Semiconductor Devices
Depositing User: Mr. Rohit Singh
Date Deposited: 23 May 2013 08:51
Last Modified: 23 May 2013 08:51

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